module counter_8bit(Clk, Rst_n, Cin, Data, Load, Count, Out);

	input Clk;				//时钟信号
	input Rst_n;				//复位信号
	input Cin;		//输入进位信号
	input [7:0] Data;			//置位数据
	input Load; 				//置位信号
	output reg[7:0] Count;		//8位计数器输出
	output reg Out;	//输出进位信号
	
	//计数器的逻辑
	always@(posedge Clk or negedge Rst_n) begin
		if(Rst_n == 1'b0) begin
			Count <= 8'b0000_0000;	//如果重置，计数器归零
			Out <= 1'b0;	//输出进位信号清零
		end 
		else begin
			if(Load == 1'b1) begin
				Count <= Data;
			end
			else if(Count == 8'b1111_1111) begin
				Count <= 8'b0000_0000;	//达到最大值或接收到输入进位信号时归零
				Out <= 1'b1;	//产生输出进位信号
			end
			else begin
				Count <= Count + 1'b1 + Cin;	//否则计数加1
				Out <= 1'b0;						//输出进位信号保持为低
			end
		end
	end
	
endmodule
